AMD is currently preparing its next massive leap in computing power with the upcoming Zen 6 architecture. Recently, enthusiasts discovered early engineering samples of these “Venice” codenamed datacenter processors appearing on OpenBenchmark.org. A user named Olrak29_ on X first spotted the listings, which detailed six different test results for these unreleased chips. These early samples offer our first real look at how AMD plans to structure its future EPYC server hardware.
The leaked data reveals that AMD is testing a wide variety of configurations using test platforms codenamed Congo, Kenya, and Nigeria. These chips come in many different core counts, ranging from a modest 64-core model to a staggering 192-core version. The Congo and Nigeria platforms even supported multi-CPU setups, where two processors worked together in a single system. This confirms that AMD intends to keep pushing the boundaries of what data centers can handle in terms of total core density and raw parallel processing.
By analyzing the structure of these chips, experts can see that AMD is using high-density “CCD” chiplets to pack more cores into the same physical space than ever before. The 64-core and 128-core versions seem to use 32 cores per chiplet, while the 192-core version uses 24 cores per chiplet. This design strategy points toward the use of Zen 6c cores, which are optimized specifically for density and efficiency. While AMD has not yet released official technical documents, these findings align with rumors that the company wants to maximize the number of cores on every single piece of silicon.
Beyond just raw core counts, these engineering samples provide a glimpse into the performance targets for the Venice line. One of the 64-core chips reached a clock speed of 3.54GHz during testing. While this is only an early sample, it shows that the architecture is already functional enough to run demanding benchmarks. AMD aims to release the final Zen 6 architecture in 2027, with flagship datacenter parts expected to feature up to 256 cores. This hardware will run on the new SP7 socket, which also promises a massive jump in memory bandwidth compared to the current Turin generation.
One of the most exciting aspects of the Zen 6 architecture is the internal cache layout. Reports suggest that AMD will increase the L3 cache capacity to 48 MB for the standard Zen 6 cores. This extra cache helps the processor keep data closer to the execution units, which is critical for high-performance computing and artificial intelligence workloads. By increasing both the core count and the cache size, AMD is clearly positioning its EPYC processors to dominate the data center market for several years to come.
Interestingly, AMD seems to be changing its typical product launch strategy. In past generations, the company usually introduced its consumer-focused processors first, then shifted its focus to the data center. This time, AMD is putting the spotlight on the EPYC server chips. The company has officially committed to a 2026 release for the Venice datacenter line, but we have heard almost nothing about “Olympic Ridge,” the codename for the upcoming consumer Zen 6 chips.
This move makes perfect sense given the current climate in the technology industry. Demand for data center hardware is exploding due to the massive growth of artificial intelligence and cloud computing. By prioritizing the EPYC “Venice” line, AMD is effectively chasing the money where the demand is highest. While gamers and home users might have to wait a bit longer to see Zen 6 in their personal desktops, businesses will likely get their hands on these powerful 256-core server monsters first. It is an aggressive strategy that highlights AMD’s focus on maintaining its competitive edge against its rivals in the server space.
